The present invention generally relates to the computer art. More particularly, the present invention relates to maintaining the integrity of information stored in a memory in a computer. Specifically, the present invention provides an improved technique for maintaining or refreshing information stored in a dynamic random access memory which enhances system performance.
As is well known, data or information stored in a dynamic random access memory (DRAM) must be refreshed or updated periodically to preserve the integrity of the information. The time period between refreshing operations varies from manufacturer to manufacturer and with the size of the memory chip. A typical refresh specification for a 256K DRAM may be 4 mSec., while a 1M DRAM may have a specification of 8 mSec or more. Accordingly, each row of DRAM must be addressed and refreshed once every specified period., e.g. 4 mSec., or the integrity of the data stored in the DRAM cannot be assured.
The typical home computer or personal computer system accomplishes DRAM refresh by addressing an individual row of the DRAM, e.g. by driving the row address strobe (RAS) line for the DRAM active, once every approximately 15 .mu.Sec. This corresponds to the refresh clock rate. Alternately, reading a row in the DRAM will accomplish the refreshing of the data stored in the row.
Although this typical method of refreshing has proven successful in most operations, it suffers from significant drawbacks in some applications. One area of insufficiency lies in the non-active computer time associated with the individual refreshing operations. Each time a refresh operation is to be done, the system must wait for completion of ongoing operations and obtain control of the appropriate address bus and control lines. Depending upon the system status at the time of a refresh request signal, the total period for completing a refresh operation of a single row may be significantly longer than the minimum time necessary--although the time elapsed for each actual refresh operation will remain about the same. As refresh operations are crucial to integrity, they typically enjoy the highest bus access priority in the computer system. The likelihood of extending the refresh time beyond the minimum necessary, thus, decreases system performance. Also, the overall system speed can become limited by the constant need to tie up the bus for a refresh operation every 15 .mu.Sec., with the attendant bus acquisition and transfer delays. Further, repeatedly driving the RAS line inactive every 15 .mu.Sec at the completion of a refresh cycle increases the risk of a "page miss" in addressing, which requires the introduction of wait states and in turn slows the overall system speed.
Accordingly, a principal object of the present invention is to provide an improved technique for maintaining integrity of data in a DRAM which generally overcomes the deficiencies of the prior art.
A more detailed object of the present invention lies in providing a method for DRAM refresh which increases the overall system operating speed.
Another object lies in providing a method of DRAM refresh having improved efficiency.
Yet another object may be found in providing a method for refresh of DRAM which also facilitates information addressing functions, including page addressing operations while maintaining compliance with typical DRAM specifications.
In further object of the present invention may be found in providing a method for DRAM refresh that optimizes bus time utilization in a personal computer system.